Scaling the dimensions of memory arrays and cells typically affects operational characteristics of memory devices formed using specific memory technologies. In some memory technologies, a reduction in the size of array lines (e.g., word lines or bit lines) normally gives rise to reductions in the cross-sectional area of conductive paths, which, in turn, increase the resistivity of the array lines. The increased resistance of the array lines may produce a reduction of voltage (e.g., voltage drops) along those lines as a function of, for example, the amount of memory cells conducting current from the array lines. Scaled dimensions of memory arrays provide also for an increased number of memory cells per word line and/or bit line. Thus, the increased number of memory cells will increase the leakage current seen on array lines, further increasing the voltage drops on array lines. Further, the reduced dimensions (e.g., reduced pitch and other circuit features) and increased number of memory cells may exacerbate the difficulties in designing and/or laying out peripheral circuitry, such as a decoder or any other memory access-related circuit.
At least some conventional memory architectures, such as those including dynamic random access memory (“DRAM”) technologies and Flash memory technologies, typically include non-ohmic devices as part of metal oxide semiconductor (“MOS”) transistors or structures. A non-ohmic device is a circuit element that can block current from passing through a respective memory cell for certain parameters (e.g., during read operations) that might affect an unselected memory cell. Examples of non-ohmic devices include diodes and transistors, such as a MOS-based gate. Such gates operate to open and close conductive paths between the word lines (or bit lines) and the portions of the memory cells used as storage. When one of the conventional memory cells is unselected, its gate is in an “off” mode of operation and conducts negligible to no current. The gate structures used in conventional memory architectures typically buffer the conventional memory cells from the affects of possible leakage currents. The above-described memory architectures and technologies, while functional for their specific technologies, are not well suited to address the scaling of memory array dimensions and cell dimensions for other memory technologies.
It would be desirable to provide improved systems, integrated circuits, and methods that minimize one or more of the drawbacks associated with conventional techniques for facilitating memory operations in an improved memory architecture for resistive memory elements.
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